VHDL "Digital Lock" design implemtntation on Altera DE2 board and Area and Time optimization of ASIC "FIFO" design using Synopsys design compiler

Part 1: In this the main objective of the project was to produce a VHDL design which can be programmed on Altera DE2 board. This project gives an overview of how different components of DE2 board can be interfaced. This project uses the various part of DE2 board like LCD screen, LEDs , Push Buttons, 7-segment display etc. Part 2: In this the main objective of the project was to produce ASIC design and optimize the design using synopsys tool. This optimization is done using 90nm technology. The target was to create design of asynchronous FIFO for n-bit wide (using parameter) data. Whose default width is 16 bits. Since it is asynchronous it's input clock chosen is 200 MHz and output clock is 40 MHz. In this data arrive in 32 word (n-bit wide) bursts. This interface signals to the transmitting device when it is clear to send a burst. This design was synthesized and simulated at the gate level. This design was optimized for time and area.