dc.contributor.advisor |
Wolfe, William |
en |
dc.contributor.author |
Portugal, Susan |
en |
dc.date.accessioned |
2015-01-22T00:53:17Z |
en |
dc.date.available |
2015-01-22T00:53:17Z |
en |
dc.date.copyright |
2014 |
en |
dc.date.issued |
2015-01-21 |
en |
dc.identifier.uri |
http://hdl.handle.net/10211.3/133567 |
en |
dc.description.abstract |
Manufacturers often resort to Application-Specific Integrated Circuits (ASIC) to meet their specific end-product requirements. Although ASICs are very effective in many applications, they have significant limitations. In particular, designers are often faced with a performance slash cost trade- off. To get the performance they desire, designers often come up with costly ASIC designs. This clash between cost and performance has encouraged the evolution of new technology, pushing toward a more flexible, cost-effective, solution. This thesis will demonstrate how the integration of specialized hardware, Field-Programmable Gate Arrays (FPGA), programmed as a pulse monitor for capturing digital signals, and a graphical user interface (GUI) can provide low a cost solution with greater flexibility, increased data collection/storage, improved portability, higher efficiency, and enhanced performance. |
en |
dc.description.statementofresponsibility |
by Susan Portugal |
en |
dc.language.iso |
en_US |
en |
dc.rights |
All rights reserved to author and California State University Channel Islands |
en |
dc.subject |
Computer Science thesis |
en |
dc.subject |
Field programmable gate arrays |
en |
dc.subject |
Digital signal processing |
en |
dc.subject |
Graphical user interfaces |
en |
dc.subject |
Computer architecture |
en |
dc.subject |
Computer Science |
en |
dc.title |
FPGA Pulse Monitor in a Laboratory Test Environment |
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dc.type |
Thesis |
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dc.contributor.department |
Computer Science |
en |
dc.contributor.committeeMember |
Bieszczad, Andrzej |
en |
dc.contributor.committeeMember |
Smith, Peter |
en |